Synopsys, Inc., an American company, is the leading company by sales in the Electronic Design Automation industry. Synopsys’ first and best-known product is Design Compiler, a logic-synthesis tool.
What You Will Do
The candidate will be responsible for validation of Emulation tool.
The Engineer will also design and develop tests in VHDL/Verilog/System Verilog languages to validate the tool
Responsible for analyzing benchmarks & in-house, modifying block-level test benches, executing verification plans, debugging RTL and gate-level simulation failures, performing gate-level simulations, interacting with R&D and CAE teams.
What you required
The successful candidate will have B.Tech / M. Tech with 0-2 years of digital design experience in the industry and hands-on experience in emulation/simulation.
Knowledge of areas like Synthesis, simulation, verification, place and route, design reuse and/or physical design is preferred.
Knowledge and experience on Hardware emulation tool or experience in verification technology, test case creation, simulation using VCS or other simulators, debugging with Verdi/DVE, familiarity with scripting languages is a plus along with good organization and communication skills for interacting with R&D and CAEs teams.